A ROBUST UART ARCHITECTURE BASED ON RECURSIVE RUNNING SUM FILTER FOR BETTER NOISE PERFORMANCE

Introduction

Serial communication is an essential to computers and allows them to communicate with the low speed peripherals devices such as keyboard the mouse, modems etc. Thus the Universal Asynchronous Receiver Transmitter is the most important component required in serial communication.

The Universal Asynchronous Receiver/Transmitter (UART) controller is the key component of the serial communications subsystem of a computer. The UART takes bytes of data and transmits the individual bits in a sequential fashion. At the destination, a second UART re-assembles the bits into complete bytes.

Serial transmission is commonly used with modems and for non-networked communication between computers, terminals and other devices.

There are two primary forms of serial transmission: Synchronous and Asynchronous. Depending on the modes that are supported by the hardware.

Some common acronyms are:

• UART Universal Asynchronous Receiver/Transmitter

• USART Universal Synchronous-Asynchronous Receiver/Transmitter

Universal Asynchronous Receiver Transmitter (UART) is used for asynchronous serial data communication between remote embedded systems. Standard UART cores utilize three mid-bit samples to decode the serial data bit and the sampling rate is derived from external timer module. But if the physical channel is noisy then data bits get corrupted during transmission and it leads to wrong data decoding at receiver. To overcome the noise problem a digital low pass filter based architecture is proposed. Recursive Running Sum (RRS) is simple low pass filter, it can be used to remove noise samples from data samples at receiver. Serial receive data signal is directly sampled with system clock and samples are fed to RRS filter. The window size of the filter is user programmable and it decides baud rate.   

VIDEO DEMO

RESEARCH ON FAST SUPER-RESOLUTION IMAGE RECONSTRUCTION BASE ON IMAGE SEQUENCE

Introduction

A lot of application situation need to obtain high resolution video and image, such as astronomy, remote sensing, martial monitor and medical diagnosis (CT,MRI) etc. Due to imaging condition and imaging mode constrain the usual imaging system to obtain high resolution image. Therefore, Obtaining observation image require amplifying processing, Although people can directly obtain high resolution image by enhancing pixel number of the charge coupled device, this method only apply very limited situation. The main reason is high cost and physic difficult to achieve. Traditional single frame scaling algorithm like Nearest Neighbors and Bilinear Interpolation has realized amplifying for one Image. But this algorithm not providing more useful information and actually not improving the resolution of image. 

Due to the continuous image frames including large number similar but not identical information, thus super-resolution image can be reconstructed according to image sequence. A group of low-resolution image sequence which has the same description of scene but each of containing different information is used to reconstruct high-resolution image. The technology is called super-resolution image reconstruction. In 1984 Tsa and Huang first presented super-resolution reconstruction base on the translation image sequence and given reconstruct method base on the frequency domain approximation. It resolved the problem of nonunique solution for the super-resolution image. So far variety algorithms include frequency, project on convex set (POCS), Maximum a Posteriori (MAP) etc have been presented. The study group of MDSP presented super-resolution reconstruction method based on the L1- norm and Bilateral Total Variation (BTV). 

VIDEO DEMO

VARIABLE BLOCK SIZE MOTION ESTIMATION HARDWARE FOR VIDEO ENCODERS

INTRODUCTION

Multimedia has experienced massive growth in recent years due to improvements in algorithms and technology. An important underlying technology is video coding and in recent years, compression efficiency and complexity have also improved significantly. Applications of video coding have moved from set-top boxes to internet delivery and mobile communications. H.264/AVC is the latest video coding standard adopting variable block size, quarter-pixel accuracy, motion vector prediction and multi-reference frames for motion estimations. These new features result in higher computation requirements than that for previous coding standards. In this thesis, we propose a family of motion estimation processors to balance tradeoffs between the performance, area, bandwidth and power consumption on an field programmable gate array (FPGA) platform. In this method a combination of algorithmic and arithmetic optimizations for motion estimation is used. At the algorithmic level, we compare different algorithms and analyze their complexities. At the arithmetic level, we explore bit-parallel and bit-serial designs, which employ non-redundant and redundant number systems. In our bit-serial design, we study tradeoffs between least significant bit first (LSB-first) and most significant first (MSB-first) modes. 

Finally, we offer a library of motion estimation processors to suit different applications. For bit-parallel processors, we offer 1-dimensional, 2-dimensional systolic based architectures. Together with tree architectures and our proposed bit-serial architecture, our family of processors is able to cover a range of applications. The bit-serial processor is able to support full search, three step search and diamond search. An early termination scheme has been introduced to further shorten the encoding time, and the standard technique is further optimized via H.264/AVC motion vector prediction

VIDEO DEMO