INTRODUCTION
Multimedia has experienced massive growth in recent years due to improvements in algorithms and technology. An important underlying technology is video coding and in recent years, compression efficiency and complexity have also improved significantly. Applications of video coding have moved from set-top boxes to internet delivery and mobile communications. H.264/AVC is the latest video coding standard adopting variable block size, quarter-pixel accuracy, motion vector prediction and multi-reference frames for motion estimations. These new features result in higher computation requirements than that for previous coding standards. In this thesis, we propose a family of motion estimation processors to balance tradeoffs between the performance, area, bandwidth and power consumption on an field programmable gate array (FPGA) platform. In this method a combination of algorithmic and arithmetic optimizations for motion estimation is used. At the algorithmic level, we compare different algorithms and analyze their complexities. At the arithmetic level, we explore bit-parallel and bit-serial designs, which employ non-redundant and redundant number systems. In our bit-serial design, we study tradeoffs between least significant bit first (LSB-first) and most significant first (MSB-first) modes.
Finally, we offer a library of motion estimation processors to suit different applications. For bit-parallel processors, we offer 1-dimensional, 2-dimensional systolic based architectures. Together with tree architectures and our proposed bit-serial architecture, our family of processors is able to cover a range of applications. The bit-serial processor is able to support full search, three step search and diamond search. An early termination scheme has been introduced to further shorten the encoding time, and the standard technique is further optimized via H.264/AVC motion vector prediction
VIDEO DEMO
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