DESIGN AND IMPLEMENTATION OF AN FPGA-BASED REAL-TIME VERY LOW RESOLUTION FACE RECOGNITION SYSTEM
Very Low Resolution Face Recognition Problem
This both projects addresses the very low resolution (VLR) problem in face recognition in which the resolution of the face image to be recognized is lower than 16 16. With the increasing demand of surveillance camera-based applications, the VLR problem happens in many face application systems.
Existing face recognition algorithms are not able to give satisfactory performance on the VLR face image. While face super-resolution (SR) methods can be employed to enhance the resolution of the images, the existing learning-based face SR methods do not perform well on such a VLR face image. To overcome this problem, this project proposes a novel approach to learn the relationship between the
high-resolution image space and the VLR image space for face
SR.
Based on this new approach, two constraints, namely, new data and discriminative constraints, are designed for good visuality and face recognition applications under the VLR problem, respectively. Experimental results show that the proposed SR
algorithm based on relationship learning outperforms the existing
algorithms in public face databases.
Design files can be downloaded from below link and for understanding purpose
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